Faraday Technology Corporation, the leader in ASIC design service and IP research and development, announced the launch of a universal physical layer IP that can support the third to fifth generation DDR/LPDDR, suitable for the telecommunications 22...
Faraday Technology Corporation, the leader in ASIC design service and IP research and development, announced the launch of a universal physical layer IP that can support the third to fifth generation DDR/LPDDR, suitable for the telecommunications 22ULP and 14FFC FinFET processes.
Zhiyuan pointed out that the company is constantly committed to providing optimized own IP solutions to help ASIC customers improve development efficiency, product cost competition and reduce risks.
Lin Shi-hyun, manager of Zhiyuan Technology, pointed out that with the increasing complexity of SoC design, the market's demand for high-performance and low-power memory solutions has been increasing. Zhiyuan provides a complete DDR/LPDDR IP solution covering control circuits, physical layers and subsystem integration services, helping customers accelerate design processes, reduce development risks, and meet the design needs of advanced applications with a high-quality and reliable memory subsystem.
Zhiyuan's DDR/LPDDR physical layer IP solution has been widely used in multiple SoC designs. After silicon verification and single chip system integration verification, its high stability and compatibility are fully in line with JEDEC regulations, which can ensure the transfer performance between memory chips and optimize power consumption performance.
Among them, the 22ULP PHY supports operating voltage as low as 0.8V, which is especially suitable for power-sensitive applications such as mobile devices, 5G and Internet of Things. The 14nm PHY supports DDR5/LPDDR5, providing transmission rates up to 6,400Mbps, and built-in parameters adjustment mechanism, impedance matching correction and DFE to ensure the quality and stability of signal transmission.
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